this tutorial deals with:

• system integration of hardware components for SoC development with Qsys
• tools for software application profiling
• design of a Nios II system equipped with a performance counter
• use of the performance counter API in a well-known example: delay computation on a sequence of Collatz trajectories, with user input of the sequence length
• HW/SW integration through BSP generation in the Monitor Program, compilation, loading on FPGA, debugging, and execution
• lab experience:
  • design and implementation of a HW/SW system with similar structure and features as those of the example presented in this tutorial, using the same development and profiling tools, but for a different application

development of a SoC with applications is a typical HW/SW codesign activity

• it consists of design and development of components of both kinds, as well as their integration to form a single system

the Quartus tool utilized in this lab tutorial for the integration of hardware components in SoC development is Qsys

• it is advised to consult the introduction to Qsys and to re-run the therein provided example on the DE1-SoC, as proposed in the first part of the previous lab tutorial, to get familiar with using the tool

a slightly more complex example is the subject of the present tutorial:

• development of a SoC similar to the aforementioned one, but equipped with a component that enables accurate profiling of software applications (see next)
• development of a software implementation of the delay computation of Collatz trajectories, and of a software application to measure its execution time

profiling a program: measuring the time spent in different parts of the program, to identify those which are critical to execution speed

• useful in HW/SW codesign to figure out which program parts may deserve possible hardware acceleration, thence to estimate the achievable speedup

the figure shows the Qsys contents of the Nios II system with Performance Counter Unit

• the scheme is similar to that of the example in the introduction to Qsys, except for the absence of the LEDs PIO and the presence of the profiling component

the C function in the figure is a software implementation of the delay computation of a Collatz trajectory with given start point

• the preprocessing directives, except the fourth one, relate to the hardware platform previously built with Qsys, see next

unlike the previous lab experiences relating to hardware implementations of the subject function, the user input here determines the length of the sequence of trajectories to be generated in the main program, that is the number of function invocations

• the switches input is multiplied by a scale factor, to get a reasonable test duration

the preprocessing directives, previously shown, enable the use of the performance counter API as well as of other symbols (SWITCHES_BASE in this case) defined in the software interface of the system built with Qsys

C source-level debugging is also available in the Monitor Program (visualization of values of variables)

• this requires compilation with optimization level -O0

the program disassembly remains accessible anyway, where to set breakpoints and to examine its execution status at critical points for correctness verification

• for example, with breakpoints as in the figure, one may check the correctness of the computed no. of iterations and of the clock frequency, resp. in r18 and r19

the proposal aims at the design and implementation of a HW/SW system with similar structure and features as those of the example presented in this tutorial, using the same development and profiling tools, but for a different application; precisely, the work goes about:

• building a Nios II system on FPGA, equipped with a performance counter component for application profiling
• software development of a coprimality test program, using a GCD computation function while processing a sequence of number pairs
• HW/SW integration of system and application, with: application profiling using the API of the aforementioned component, BSP generation, compilation, loading and execution on the FPGA, with debugging if needed

recommended readings:

• Introduction to the Qsys System Integration Tool - For Quartus Prime 16.1, Intel Corp. - FPGA University Program, November 2016

readings for further consultation:

• Profiling Nios II Systems, AN-391-3.0, Altera Corp., July 2011

useful materials for the proposed lab experience:

• Performance Counter Unit Core, Ch. 36 in: Embedded Peripherals IP User Guide, Intel Corp., UG-01085 | 2019.12.16
• Intel FPGA Monitor Program Tutorial for Nios II - For Quartus Prime 16.1, Intel® FPGA University Program (November 2016)
• source files for running the lab experience