single-clock synchronous digital circuits, composed of an interconnection of:

• combinational logic
• flip-flops

thus also including widely used components such as: registers, adders, multiplexers etc.

• abstraction level: clock cycles, RTL models

what cannot be modeled: asynchronous hardware, HW with latches, multi-phase clocked HW etc.

• RTL models are adequate in a great deal of practical cases, viz. to describe hardware implementations of algorithms

example:

Schaumont, Fig. 1.1 - Models and behaviour of a hardware component

the code generator of the Gezel platform yields a translation into synthesizable VHDL

lab experience:

1. install the Gezel base software and its VHDL code generator
2. get the source file collatz.fdl containing the Gezel example description
3. run the translation from the command line: fdlvhd collatz.fdl
4. install Quartus Prime Lite 16.1 by Intel Corp., launch it, and then in this system:
5. create a new Quartus project named collatz
6. copy the .vhd files produced by step 3 into the project directory
7. assign the aforementioned files to the project and compile
8. check any error or warning messages
9. set the clock to a frequency that warrants a positive value for the worst-case slack
10. create test waveforms for the collatz circuit, with clock input corresponding to the frequency established in the previous step and value 27 for the trajectory start
11. run the functional simulation
12. repeat the simulation for different trajectory starts

recommended readings:

• Schaumont (2012) Cap. 1, Sez. 1.1.1; App. A.1
• Quartus Prime Introduction Using VHDL Designs - For Quartus Prime 16.1; Intel FPGA University Program
• Using TimeQuest Timing Analyzer - For Quartus Prime 16.1, Sect. 1-2, 4; Intel FPGA University Program
• Introduction to Simulation of VHDL Designs - For Quartus Prime 16.1; Intel FPGA University Program

for further consultation:

• Schaumont (2012) App. A.2

other useful material for the proposed lab experience:

• Gezel installation manual
• Quartus Prime Lite 16.1 download
• Intel FPGA University Program Installer