Tips on editing Quartus Prime Schematic diagrams  

1. Imperfect wiring, multiple node/bus names, use of "wire" gates

  Wiring of node (single-bit) or bus lines to device I/O ports as well as 
line or bus forking or joining must be made very carefully, for imperfect 
wiring is no wiring. Imperfect wiring is marked in the BDF schematic by 
a fat X near the desired wiring point, whereby often the easiest solution 
is to delete a nonmatching line and then to redraw it. 

  Proper naming of a bus or indexed line (e.g. x[0] for the lowest line of 
bus x) is highly relevant to diagram correctness. Forking as well as joining 
must employ the same bus name on all lines it applies to. On the other hand, 
whenever a static shift by wiring is desired, e.g. to map an x[h+l..l] bus 
to a y[h..0] bus, the wiring must go through a "wire" gate, otherwise a bus 
with multiple names would result. The schematic on slide 7 of lab tutorial E02 
has an example of such a case.


2. Bus naming rules in Block Diagram/Schematic files (.bdf) 

In some cases, indexed names of bus or node (single-bit) lines may cause the 
following to show up in the compilation report:

   Warning (275080): Converted elements in bus name "<name>" using legacy naming rules.
   Make any assignments on the new names, not on the original names.

which may result in compilation errors at a later stage.
Fix: see https://forums.intel.com/s/feed/0D50P00003yyN41SAE

  The same fix as well as another one is found in Quartus by the
Help > Message list page for the quoted message. The alternative fix is:

   You can also update your BDF file to use Quartus II naming rules by
   clicking Save As, then choosing
      Block Diagram/Schematic File using Quartus II naming rules (*.bdf)
   and then saving it.

--

   Author: Giuseppe Scollo, University of Catania, DMI
   Version: 3
   Date: 12 October 2019