Clock fine tuning tips using Quartus Quartus TimeQuest Analysis After successful compilation of a Quartus project for a synchronous circuit or system, if no errors are reported (check Messages under Analysis & Synthesis in the central pane Table of Contents), one should adjust the clock frequency in order to get a positive worst-case slack. This fine tuning may be easily performed by means of the Quartus tool TimeQuest Timing Analyzer. Here are the actions to this purpose: 1. under TimeQuest Timing Analyzer in the Table of Contents, click Clocks, then right-click CLK in the right pane and finally select Report Timing... (in TimeQuest UI); 2. in the Report Timing window which pops up, select CLK for the From clock top entry, then press the Report Timing bottom button; 3. the worst case slack is reported in the bottom Console pane; it's OK if this is positive, otherwise (a negative slack is reported in red) one should increase the current clock period (default is 1 ns) at least by the absolute value of the reported worst-case slack, as follows: 4. again under TimeQuest Timing Analyzer in the Table of Contents, click Clocks, then right-click CLK in the right pane and finally select Edit Clock Constraint... (in TimeQuest UI); in the Create Clock window that then pops up, adjust the Period, Rising (half of Period) and Falling (equal to Period) times as desired, then press Run, close the TimeQuest Timing Analyzer while answering positively to the request whether to save the output SDC file; 5. then, back to the Quartus window, assign the generated SDC file to the project, save the project, recompile and repeat until step 3: if a proper adjustment was made, a positive worst case slack should be reported, otherwise further widen the clock period as explained. -- Author: Giuseppe Scollo, University of Catania, DMI Version: 1 Date: 15 October 2017