Schaumont, Figure 5.5 - Mealy FSM of a recognizer for the pattern ‘110’

Schaumont, Figure 5.6 - Moore FSM of a recognizer for the pattern ‘110’

Schaumont, Table 5.4 - Behavior of the FSMD in Listing 5.13

dp euclid(in m_in, n_in : ns(16);
                out gcd : ns(16)) {
  reg m, n : ns(16);
  reg done : ns(1);
  sfg init { m = m_in;
                n = n_in;
                done = 0;
                gcd = 0; }
  sfg reduce {   m = (m >= n) ? m - n : m;
                        n = (n > m) ? n - m : n; }
  sfg outidle {   gcd = 0;
                        done = ((m == 0) | (n == 0)); }
  sfg complete{ gcd = ((m > n) ? m : n);
                        $display(‘‘gcd = ’’, gcd); }
}

Schaumont, Listing 5.14 - Euclid’s GCD as an FSMD

fsm euclid_ctl(euclid) {
  initial s0;
  state s1, s2;
  @s0 (init) -> s1;
  @s1 if (done) then (complete) -> s2;
                         else (reduce, outidle) -> s1;
   @s2 (outidle) -> s2;
}

control elements introduced with the FSM: almost all those proposed in the previous lab experience

N.B.: the execution of reduce and outidle fired by the FSM in state s1 is concurrent

dp updown_ctl(in a_sm_3, a_gt_0 : ns(1);
                         out instruction : ns(2)) {
  reg state_reg : ns(2);
  // state encoding: s0 = 0, s1 = 1, s2 = 2
  // instruction encoding: clr = 0, inc = 1, dec = 2
  always {
    state_reg  = (state_reg == 0) ? 1 :
                        ((state_reg == 1) & a_sm_3) ? 1 :
                        ((state_reg == 1) & ˜a_sm_3) ? 2 :
                        ((state_reg == 2) & a_gt_0) ? 2 : 1;
    instruction = (state_reg == 0) ? 0 :
                        ((state_reg == 1) & a_sm_3) ? 1 :
                        ((state_reg == 1) & ˜a_sm_3) ? 2 :
                        ((state_reg == 2) & a_gt_0) ? 2 : 1;
  }
}

Schaumont, Listing 5.15 - FSM controller for updown counter using expressions

a comparison with the example description in Listing 5.13 shows:

• a greater descriptive complexity, and
• the need to introduce a numerical encoding of states rather than a symbolic one

on the other hand, separate descriptions of controller and datapath by expressions may be combined into a single description, whereby some performance enhancement may be gained

• for example, latency may often decrease by one clock cycle, since state transition conditions, which need to be evaluated on registers in the FSMD model, in a single description may be generated and evaluated within the same clock cycle
• however, as we are going to see, besides this advantage other shortcomings show up

dp updown_ctl(out c : ns(3)) {
  reg a : ns(3);
  reg state : ns(2);
  sig a_sm_3 : ns(1);
  sig a_gt_0 : ns(1);
  // state encoding: s0 = 0, s1 = 1, s2 = 2
  always {
    state = (state == 0) ? 1 :
                ((state == 1) & a_sm_3) ? 1 :
                ((state == 1) & ˜a_sm_3) ? 2 :
                ((state == 2) & a_gt_0) ? 2 : 1;
    a_sm_3 = (a < 3);
    a_gt_0 = (a > 0);
    a = (state == 0) ? 0 :
          ((state == 1) & a_sm_3) ? a + 1 :
          ((state == 1) & ˜a_sm_3) ? a - 1 :
          ((state == 2) & a_gt_0) ? a + 1 : a - 1;
    c = a;
  }
}

Schaumont, Listing 5.16 - updown counter using expressions

the comparison of the two-part FSMD description given in Listings 5.12 and 5.13 with this monolithic description shows that in the latter:

• the mingling of data processing aspects with scheduling, sequencing and control aspects complicates the understandability of the overall design
• the monolithic integration of these aspects also makes it harder the reusability of parts of the description
  • for example, reuse of the datapath under a different scheduling

on the other hand, single description offers more optimization opportunities:

• of state assignments, whereas they are automatically generated by synthesis tools in the other case
• of applications where control has a little influence, whereas much greater is the influence of high-throughput requirements

for complex, highly structured applications, FSMD description with separate FSM and datapath descriptions seems to be preferable