both the coprocessor instruction set and the specific coprocessor interface depend on the type of processor—not all processors have a coprocessor interface

• the decision of using a specific coprocessor interface locks the custom hardware module into a particular processor, thus it limits the reusability of that custom hardware module to systems that also use the same processor

main advantages of a coprocessor interface over an on-chip bus:

• higher throughput : because not constrained by the wordlength of the bus on chip, nor by the load/store transfer mechanism
• fixed latency : a coprocessor bus is a dedicated, point-to-point connection with stable, predictable timing

the integration of hardware and software can be considerably accelerated as follows:

1. reserve a portion of the opcodes from a microprocessor for new instructions
2. integrate the custom-hardware modules directly into the micro-architecture of the micro-processor
3. control the custom-hardware modules using new instructions derived from the reserved opcodes

the resulting design is called an Application-Specific Instruction-set Processor (ASIP)

• while a coprocessor instruction set is part of a microprocessor, an ASIP instruction set is defined by the application

ASIP design automates some of the more difficult aspects of HW/SW codesign:

• the instruction-fetch and dispatch mechanism in the micro-processor ensures that custom-hardware and software remain synchronized
• design of an ASIP proceeds in an incremental fashion, that helps the designer to avoid drastic changes to the system architecture while exploring different options

Schaumont, Figure 11.12 - ASIP design flow

sequential ASIP design does not generally deliver better performance than SoC design based on custom hardware modules, yet it does deliver less error-prone results

• significant progress has been made on design tools that support the ASIP design flow—all of the shaded boxes in the figure can be obtained as commercial tools

the Nios-II softcore processor has a coprocessor interface whereby custom instructions may be defined and hardware modules may be attached to

Schaumont, Figure 11.15 - Nios-II custom-instruction interface timing

the interface supports variable-length execution of custom instructions through a two-way handshake

the clk_en input is used to mask off the clock to the custom hardware when the instruction is inactive

• the software instruction custom commands its execution, e.g.:
  • custom 0x5, r2, r3, r5
  assigns the value 0x5 to n and associates the dataa, datab, result ports with registers r2, r3, r5, respectively—use of n: to multiplex different custom instructions in the hardware module

the use of a local register file in the custom hardware module is also supported